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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. o3112hk 20120919-s00009/51407hkim 20070328-s00008,s00009 no.a0788-1/22 lc72131k LC72131KMA overview the lc72131k and LC72131KMA are pll frequency synthesizers for use in tuners in radio/cassette players. they allow high-performance am/fm tuners to be implemented easily. features ? high speed programmable dividers ? fmin: 10 to 160mhz ?????? ??.. pulse swallower (built-in divide-by-two prescaler) ? amin: 2 to 40mhz ?????????. pulse swallower 0.5 to 10mhz ????????.. direct division ? if counter ? ifin: 0.4 to 12mhz ?????????. am/fm if counter ? reference frequencies ? twelve selectable frequencies (4.5 or 7.2mhz crystal) ? 100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1khz ? phase comparator ? dead zone control ? unlock detection circuit ? deadlock clear circuit ? built-in mos transistor for forming an active low-pass filter ? i/o ports ? dedicated output ports: 4 ? input or output ports: 2 ? support clock time base output ? serial data i/o ? support ccb format communicatio n with the system controller. continued on next page. ordering number : ena0788a cmos ic pll frequency synthesizer ? ccb is a registered trademark of sanyo semiconductor co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format.
lc72131k, LC72131KMA no.a0788-2/22 continued from preceding page. ? operating ranges ? supply voltage ........................4.5 to 5.5v ? operating temperature ............ -40 to +85 ? c ? packages ? dip22s(300mil) / mfp20j(300mil) specifications absolute maximum ratings at ta = 25 ? c, v ss = 0v parameter symbol pins conditions ratings unit supply voltage v dd max v dd -0.3 to +7.0 v maximum input voltage v in 1 max ce, cl, di, ain -0.3 to +7.0 v v in 2 max xin, fmin, amin, ifin -0.3 to v dd +0.3 v v in 3 max io1 , io2 -0.3 to +15 v maximum output voltage v o 1 max do -0.3 to +7.0 v v o 2 max xout, pd -0.3 to v dd +0.3 v v o 3 max bo1 to bo4 , io1 , io2 , aout -0.3 to +15 v maximum output current i o 1 max bo1 0 to 3.0 ma i o 2 max do, aout 0 to 6.0 ma i o 3 max bo2 to bo4 , io1 , io2 0 to 10 ma allowable power dissipation pd max ta ? 85 ? c [lc72131k] 350 mw ta ? 85 ? c [LC72131KMA] 180 mw operating temperature topr -40 to +85 ? c storage temperature tstg -55 to +125 ? c note 1: power pins v dd and v ss : insert a capacitor with a capacitance of 2,000pf or higher between these pins when using the ic.
lc72131k, LC72131KMA no.a0788-3/22 allowable operating ranges at ta = -40 ? c to +85 ? c, v ss = 0v parameter symbol pins conditions ratings unit min typ max supply voltage v dd v dd 4.5 5.5 v input high-level voltage v ih 1 ce, cl, di 0.7v dd 6.5 v v ih 2 io1 , io2 0.7v dd 13 v input low-level voltage v il ce, cl, di, io1 , io2 0 0.3v dd v output voltage v o 1 do 0 6.5 v v o 2 bo1 to bo4 , io1 , io2 , aout 0 13 v input frequency fin1 xin v in 1 1.0 8.0 mhz fin2 fmin v in 2 10 160 mhz fin3 amin v in 3 2.0 40 mhz fin4 amin v in 4 0.5 10 mhz fin5 ifin v in 5 0.4 12 mhz supported crystals x'tal xin, xout note 1 4.0 8.0 mhz input amplitude high-level clock pulse width t h cl [figure 1][figure 2] 160 ns low-level clock pulse width v in 1 xin fin1 400 1500 mvrms v in 2-1 fmin f=10 to 130mhz 40 1500 mvrms v in 2-2 fmin f=130 to 160mhz 70 1500 mvrms v in 3 amin fin3 40 1500 mvrms v in 4 amin fin4 40 1500 mvrms v in 5 ifin fin5 (ifs=1) 40 1500 mvrms v in 6 ifin fin5 (ifs=0) 70 1500 mvrms data setup time tsu di, cl note 2 0.75 ? s data hold time thd di, cl note 2 0.75 ? s clock low-level time tcl cl note 2 0.75 ? s clock high-level time tch cl note 2 0.75 ? s ce wait time tel ce, cl note 2 0.75 ? s ce setup time tes ce, cl note 2 0.75 ? s ce hold time teh ce, cl note 2 0.75 ? s data latch change time tlc note 2 0.75 ? s data output time tdc do, cl differs depending on the value of the pull-up resistor. note 2 0.35 ? s tdh do, ce note 1: recommended crystal oscillator ci values: ci ? 120 ? (for a 4.5mhz crystal) ci ? 70 ? (for a 7.2mhz crystal) the characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. therefore we recommend cons ulting with the anufacturer of the crystal for evaluation and reliability. note 2: refer to "serial data timing".
lc72131k, LC72131KMA no.a0788-4/22 electrical characteristics in the allowable operating ranges parameter symbol pins conditions ratings unit min typ max built-in feedback resi stance rf1 xin 1.0 m ? rf2 fmin 500 k ? rf3 amin 500 k ? rf4 ifin 250 k ? built-in pull-down resistor rpd1 fmin 200 k ? rpd2 amin 200 k ? hysteresis vhys ce, cl, di, io1 , io2 0.1v dd v output high-level voltage v oh pd i o =1ma v dd -0.1 v output low-level voltage v ol 1 pd i o =1ma 1.0 v v ol 2 bo1 i o =0.5ma 0.5 v i o =1ma 1.0 v v ol 3 do i o =1ma 0.2 v i o =5ma 1.0 v v ol 4 bo2 to bo4 , io1 , io2 i o =1ma 0.2 v i o =5ma 1.0 v i o =8ma 1.6 v v ol 5 aout i o =1ma ain=1.3v 0.5 v input high-level current i ih 1 ce, cl, di v i =6.5v 5.0 ? a i ih 2 io1 , io2 v i =13v 5.0 ? a i ih 3 xin v i =v dd 2.0 11 ? a i ih 4 fmin, amin v i =v dd 4.0 22 ? a i ih 5 ifin v i =v dd 8.0 44 ? a i ih 6 ain v i =6.5v 200 na input low-level current i il 1 ce, cl, di v i =0v 5.0 ? a i il 2 io1 , io2 v i =0v 5.0 ? a i il 3 xin v i =0v 2.0 11 ? a i il 4 fmin, amin v i =0v 4.0 22 ? a i il 5 ifin v i =0v 8.0 44 ? a i il 6 ain v i =0v 200 na output off leakage current ioff1 bo1 to bo4 , aout, io1 , io2 v o =13v 5.0 ? a ioff2 do v o =6.5v 5.0 ? a high-level three-state off leakage current ioffh pd v o =v dd 0.01 200 na low-level three-state off leakage current ioffl pd v o =0v 0.01 200 na input capacitance cin fmin 6 pf current drain i dd 1 v dd x'tal=7.2mhz f in 2=130mhz v in 2=40mvrms 5 10 ma i dd 2 v dd pll block stopped (pll inhibit) x'tal oscillator operating (x'tal=7.2mhz) 0.5 ma i dd 3 v dd pll block stopped x'tal oscillator operating 10 ? a
lc72131k, LC72131KMA no.a0788-5/22 serial data timing package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3059a [lc72131k] 3445 [LC72131KMA] tcl teh tes thd tsu old new tlc tdh tdc tel tch when stopped with cl high v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch cl di ce ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tcl teh tes thd tsu old new tlc tdh tdc tdc tel tch ? when stopped with cl low v il v il v il v ih v ih v ih v ih v ih v ih v il v il v il do internal data latch cl di ce ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sanyo : mfp20j(300mil) 12.7 0.4 5.4 7.8 0.5 1.8 0.05 1 2 20 0.15 1.27 (0.635) sanyo : dip22s(300mil) 21.0 6.4 0.95 0.48 111 22 12 (0.8) 1.78 (3.25) 3.3 3.9 max 0.51min 7.62 0.25
lc72131k, LC72131KMA no.a0788-6/22 pin assignments block diagram io2 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 xout ifin nc amin fmin v dd pd ain aout v ss ce nc xin do cl di bo3 bo2 bo1 io1 bo4 lc72131k top view pd ifin amin ce di cl do v ss v dd fmin xout xin universal counter unlock detector phase detector charge pump reference divider data shift register latch 12bits programmable divider swallow counter 1/16,1/17 4bits power on reset ccb i/f 1/2 ain aout bo1 bo2 bo3 bo4 io1 io2 io2 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 xout ifin amin fmin v dd pd ain aout v ss ce xin do cl di bo3 bo2 bo1 io1 bo4 LC72131KMA top view
lc72131k, LC72131KMA no.a0788-7/22 pin functions symbol pin no. type functions circuit configuration lc72131k LC72131KMA xin xout 1 22 1 20 x'tal osc crystal resonator connection (4.5mhz/7.2mhz) fmin 16 14 local oscillator signal input fmin is selected when the serial data input dvs bit is set to 1. the input frequency range is from 10 to 160mhz. the input signal passes through the internal divide-by-two prescaler and is input to the swallow counter. the divisor can be in the range 272 to 65535. however, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. amin 15 13 local oscillator signal input amin is selected when the serial da ta input dvs bit is set to 0. when the serial data input sns bit is set to 1: ? the input frequency range is 2 to 40mhz. ? the signal is directly input to the swallow counter. ? the divisor can be in the range 272 to 65535, and the divisor used will be the value set. when the serial data input sns bit is set to 0: ? the input frequency range is 0.5 to 10mhz. ? the signal is directly input to a 12-bit programmable divider. ? the divisor can be in the range 4 to 4095, and the divisor used will be the value set. ce 3 2 chip enable set this pin high when inputting (di) or outputting (do) serial data. di 4 3 input data inputs serial data transferred from the controller to the lc72131k/kma. cl 5 4 clock used as the synchronization clock when inputting (di) or outputting (do) serial data. do 6 5 output data outputs serial data transferred from the lc72131k/kma to the controller. the content of the output data is determined by the serial data doc0 to doc2. v dd 17 15 power supply the lc72131k/kma power supply pin (v dd =4.5 to 5.5v) the power on reset circuit operates when power is first applied. - v ss 21 19 ground the lc72131k/kma ground - bo1 bo2 bo3 bo4 7 8 9 10 6 7 8 9 output port dedicated output pins the output states are determined by bo1 to bo4 bits in the serial data. data: 0=open, 1=low a time base signal (8hz) can be output from the bo1 pin. (when the serial data tbc bit is set to 1.) care is required when using the bo1 pin, since it has a higher on impedance that the other output ports (pins bo2 to bo4 ). io1 io2 11 13 10 12 i/o port i/o dual-use pins the direction (input or output) is determined by bits ioc1 and ioc2 in the serial data. data: 0=input port, 1=output port when specified for use as input ports: the state of the input pin is tr ansmitted to the controller over the do pin. input state: low=0 data value high=1 data value when specified for use as output ports: the output states are determined by the io1 and io2 bits in the serial data. data: 0=open, 1=low these pins function as input pins following a power on reset. continued on next page. s s s s
lc72131k, LC72131KMA no.a0788-8/22 continued from preceding page. symbol pin no. type functions circuit configuration lc72131k LC72131KMA pd 18 16 charge pump output pll charge pump output when the frequency generated by dividing the local oscillator frequency by n is higher than the reference frequency, a high level is output from the pd pin. similarly, when that frequency is lower, a low level is output. the pd pin goes to the high impedance state when the frequencies match. ain aout 19 20 17 18 lpf amplifier transistors the n-channel mos transistor used for the pll active low-pass filter. ifin 12 11 if counter accepts an input in the frequency range 0.4 to 12mhz. the input signal is directly transmitted to the if counter. the result is output starting the msb of the if counter using the do pin. four measurement periods are supported: 4, 8, 32, and 64ms. di control data (seria l data input) structure [1] in1 mode [2] in2 mode r2 r1 r0 (3) if-ctr xs cte dvs sns p15 p14 p13 p12 p11 p10 (1) p-ctr (2) r-ctr p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 r3 address 0 0 1 0 1 0 0 di 0 first data in1 test1 test0 ifs (12) test (11) ifs (10) pd-c (5) o-port (13) don?t care (6) do-c (9) time dlc tbc gt1 gt0 dz1 dz0 ul1 ul0 doc2 doc1 (7) unlock (4) io-c (8) dz-c (3) if-ctr doc0 dnc bo4 bo3 bo2 bo1 io2 io1 ioc2 ioc1 test2 address 0 0 1 0 1 0 0 di 1 first data in2
lc72131k, LC72131KMA no.a0788-9/22 control data functions no. control block/data functions related data (1) programmable divider data p0 to p15 dvs, sns data that sets the divisor of the programmable divider. a binary value in which p15 is the msb. the lsb changes depending on dvs and sns. (*: don?t care) note: p0 to p3 are ignored when p4 is the lsb. selects the signal input pin (amin or fm in) for the programmable divider, switches the input frequency range. (*: don?t care) note: see the ?programmable divider structure? item for more information. (2) reference divider data r0 to r3 xs reference frequency (fref) selection data. note *: pll inhibit the programmable divider block and the if counter block are stopped, the fmin, amin, and ifin pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. crystal resonator selection xs=0: 4.5mhz xs=1: 7.2mhz the 7.2mhz frequency is selected after the power-on reset. (3) if counter control data cte gt0, gt1 if counter measurement start data cte=1: counter start =0: counter reset determines the if counter measurement period. note: see the ?if counter structure? item for more information. ifs continued on next page. twice the value of the setting the value of the setting the value of the setting 272 to 65535 272 to 65535 4 to 4095 actual divisor divisor setting (n) lsb sns p0 p0 p4 * 1 0 1 0 0 dvs 10 to 160mhz 2 to 40mhz 0.5 to 10mhz fmin amin amin input frequency range input pin sns * 1 0 1 0 0 dvs 1 * pll inhibit * pll inhibit + x'tal osc stop 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 3 15 10 9 5 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 100khz 50 25 25 12.5 6.25 3.125 3.125 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reference frequency r0 r1 r2 r3 wait time (ms) measurement time (ms) gt0 gt1 3 to 4 3 to 4 7 to 8 7 to 8 4 8 32 64 0 1 0 1 0 0 1 1
lc72131k, LC72131KMA no.a0788-10/22 continued from preceding page. no. control block/data functions related data (4) i/o port specification data ioc1, ioc2 specifies the i/o direction for the bidirectional pins io1 and io2 . data: 0=input mode, 1=output mode (5) output port data bo1 to bo4 io1, io2 data that determines the output from the bo1 to bo4 , io1 and io2 output ports data: 0=open, 1=low the data=0 (open) state is sele cted after the power-on reset. ioc1 ioc2 (6) do pin control data doc0 doc1 doc2 data that determines the do pin output the open state is selected after the power-on reset. note: 1. end-uc: check for if counter measurement completion (1) when end-uc is set and the if counter is started (i.e., when cte is changed from zero to one), the do pin automatically goes to the open state. (2) when the if counter meas urement completes, the do pin goes low to indicate the measurement completion state. (3) depending on serial data i/o (ce: high) the do pin goes to the open state. note: 2. goes to the open state if the i/ o pin is specified to be an output port. caution: the state of the do pin during a data input period (an in1 or in2 mode period with ce high) will be open, regardless of the state of the do control data (doc0 to doc2). also, the do pin during a data output period (an out mode period with ce high) will output the contents of the internal do serial data in synchronization with the cl pin signal, regardless of the state of the do control data (doc0 to doc2). ul0, ul1 cte ioc1 ioc2 (7) unlock detection data ul0, ul1 selects the phase error ( ? e) detection width for checking pll lock. a phase error in excess of the specified dete ction width is seen as an unlocked state. note: in the unlocked state the do pin goes low and the ul bit in the serial data becomes zero. doc0 doc1 doc2 continued on next page. open the io1 pin state *2 the io2 pin state *2 open open low when the unlock state is detected end-uc *1 open do pin state doc0 doc1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 doc2 ? (1) count start (3)ce: high (2) count end do pin ? open ? e is output directry ? e is extended by 1 to 2ms ? stopped 0 ? 0.55 ? s ? 1.11 detector output ? e detection width ul0 0 1 0 1 0 0 1 1 ul1
lc72131k, LC72131KMA no.a0788-11/22 continued from preceding page. no. control block/data functions related data (8) phase comparator control data dz0, dz1 ? controls the phase comparator dead zone. dead zone width: dza lc72131k, LC72131KMA no.a0788-12/22 control data functions no. control block/data functions related data (1) i/o port data i2, i1 latched from the pin states of the io1 and io2 i/o ports. these values follow the pin states rega rdless of the input or output setting. i1 ? io1 pin state high: 1 i2 ? io2 pin state low: 0 ioc1 ioc2 (2) pll unlock data ul latched from the state of th e unlock detection circuit. ul ? 0: unlocked ul ? 1: locked or detection stopped mode ul0 ul1 (3) if counter binary counter c19 to c0 latched from the value of the if counter (20-bit binary counter). c19 ? msb of the binary counter c0 ? lsb of the binary counter cte gt0 gt1 serial data i/o methods the lc72131k/kma inputs and outputs data using the sany o ccb (computer control bus) audio lsi serial bus format. this lsi adopts an 8-bit address format ccb. i/o mode address function b0 b1 b2 b3 a0 a1 a2 a3 [1] in1 (82) 0 0 0 1 0 1 0 0 ? control data input mode (serial data input) ? 24 data bits are input. ? see the ?di control data (serial data input) structure? item for details on the meaning of the input data. [2] in2 (92) 1 0 0 1 0 1 0 0 ? control data input mode (serial data input) ? 24 data bits are input. ? see the ?di control data (serial data input) structure? item for details on the meaning of the input data. [3] out (a2) 0 1 0 1 0 1 0 0 ? data output mode (serial data output) ? the number of bits output is equal to the number of clock cycles. ? see the ?do control data (serial data output) structure? item for details on the meaning of the output data. (2) (1) first data in1/2 first data out first data out a3 a2 a1 a0 b3 b2 b1 b0 di i/o mode determined ce cl ? (2) (1) cl: normal high (2) cl: normal low (1) do ? ? ? ? ? ? ? ?
lc72131k, LC72131KMA no.a0788-13/22 1. serial data input (in1/in2) tsu, thd, tes, teh ? 0.75 ? s tlc<0.75 ? s (1) cl: normal high (2) cl: normal low 2. serial data output (out) tsu, thd, tel, tes, teh ? 0.75 ? s tdc, tdh<0.35 ? s (1) cl: normal high (2) cl: normal low note: since the do pin is an n-channel open-drain pin, th e time for the data to change (tdc and tdh) will differ depending on the value of the pull-up resist or and printed circuit board capacitance. internal data tlc teh tes tel thd tsu r3 r2 r1 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 r0 di ce cl internal data tlc teh tes tel thd tsu r3 r2 r1 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 r0 di ce cl do di ce cl tdc tdc tdh teh tes tel thd tsu ul i1 i2 a3 a2 a1 a0 b3 b2 b1 b0 c0 c1 c2 c3 do tdc tdc tdh teh tes tel thd tsu i1 i2 ul a3 a2 a1 a0 b3 b2 b1 b0 c0 c1 c2 c3 di ce cl
lc72131k, LC72131KMA no.a0788-14/22 programmable divider structure dvs sns input pin set divisor act ual divisor: n input frequency range (a) (b) (c) 1 1 0 * 1 0 fmin amin amin 272 to 65535 272 to 65535 4 to 4095 twice the set value the set value the set value 10 to 160mhz 2 to 40mhz 0.5 to 10mhz * : don't care programmable divider calculation examples (1) fm, 50khz steps (dvs=1 , sns=*: fmin selected) fm rf=90.0mhz (if=+10.7mhz) fm vco=100.7mhz pll fref=25khz (r0 to r1=1, r2 to r3=0) 100.7mhz (fmvco) ? 25khz (fref) ? 2 (fmin: divide-by-two prescaler) =2014 ? 07de (hex) (2) sw 5khz steps (dvs=0, sns=1: amin high-speed side selected) sw rf=21.75mhz (if=+450khz) sw vco=22.20mhz pll fref=5khz (r0=r2=0, r1=r3=1) 22.2mhz (sw vco) ? 5khz (fref) =4440 ? 1158 (hex) (3) mw 10khz steps (dvs=0, sns=0: amin low-speed side selected) mw rf=1000khz (if=+450khz) mw vco=1450khz pll fref=10khz (r0 to r2=0, r3=1) 1450khz (mw vco) ? 10khz (fref)=145 ? 091 (hex) (a) (c) (b) sns dvs 4bits 12bits swallow counter programmable divider fvco=fref ? n fref fvco/n pd ? e 1/2 fmin amin p0 0 p1 0 7 d e 1 p2 1 p3 1 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3 1 0 1 1 11100000*1 1 1 0 0 p0 0 p1 1 1 5 8 0 p2 0 p3 1 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3 1 0 1 0 1000100010 0 1 0 1 p0 * p1 0 9 1 * p2 * p3 * p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3 1 0 0 01001000000 0 0 0 1
lc72131k, LC72131KMA no.a0788-15/22 if counter structure the lc72131k/kma if counter is a 20-bit binary counter. the result, i.e., the counter?s msb, can be read serially from the do pin. gt1 gt0 measurement time measurement time (gt) (ms) wait time (twu) (ms) 0 0 1 1 0 1 0 1 4 8 32 64 3 to 4 3 to 4 7 to 8 7 to 8 the if frequency (fc) is measured by determining how many pulses were input to an if counter in a specified measurement period, gt. fc= (c=fc ? gt) c: count value (number of pulses) if counter frequency calculation examples (1) when the measurement period (gt) is 32ms, the count (c) is 53980 hexadecimal (342400 decimal): if frequency (fc) =342400 ? 32ms=10.7mhz (2) when the measurement period (gt) is 8ms, the count (c) is e10 hexadecimal (3600 decimal): if frequency (fc) =3600 ? 8ms=450khz 4/8/32/64ms 8 to 11 4 to 7 0 to 3 16 to 19 12 to 15 (fc) (c) (gt) gt0 m s b l s b if counter (20bits binary counter) c=fc ? c gt i2 i1 0 8 9 3 5 ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 01 0 1 0 011100110000 0 0 0 i2 i1 0 1 e 0 0 ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 00 0 0 0 000111000010 0 0 0
lc72131k, LC72131KMA no.a0788-16/22 if counter operation before starting the if count, the if counter must be reset in advance by setting cte in the serial data to 0. the if count is started by changing the cte bit in the seri al data from 0 to 1. the serial data is latched by the lc72131k/kma when the ce pin is dropped from high to low. the if signal must be supplied to the ifin pin in the period between the point the ce pin goes low and the end of the wait time at the latest. next, the value of the if counter at the end of the measurement period must be read ou t during the period that cte is 1. this is because the if counter is reset when cte is set to 0. note: when operating the if counter, the control microproce ssor must first check the state of the if-ic sd (station detect) signal and only after determining that the sd sign al is present turn on if buffer output and execute an if count operation. autosearch tech niques that use only the if counter are not recommended, since it is possible for if buffer leakage output to cause incorr ect stops at points wher e there is no station. ifin minimum input sensitivity standard f [mhz] ifs 0.4 ? f<0.5 0.5 ? f<8 8 ? f ? 12 1: normal mode 40mvrms (0.1 to 3mvr ms) 40mvrms 40mvrms (1 to 10mvrms) 0: degradation mode 70mvrms (10 to 15mvrm s) 70mvrms 70mvrms (30 to 40mvrms) note: values in parentheses are actual performance values presented as reference data. unlock detection timing unlock detection determination timing unlocked state detection is performed in the reference frequency (fref) period (interval). therefore, in principle, unlock determination requires a time longer than the peri od of the reference frequency . however, immediately after changing the divisor n (frequency) unlock detection must be performed after waiting at least two periods of the reference frequency. figure 1 unlocked state detection timing for example, if fref is 1khz, i.e., the pe riod is 1ms, after changing the divisor n, the system must wait at least 2ms before checking for the unlocked state. cte data=1 count start count end (end-uc) gt wait time measurement time ifin frequncy measurement time ce new divisor n? old divisor n new data old data note: after changing the divisor, ? error is output after two fref periods. the divisor n is not updated during the first period. n- counter ? error (unlock) data latch vco/n fref ce
lc72131k, LC72131KMA no.a0788-17/22 figure 2 circuit structure figure 3 unlocked state data output using serial data output in the lc72131k/kma, once an unlocked state occurs, the unlocked state serial data (ul) will not be reset until a data input (or output) operation is performed. at the data output (1) point in figure 3, although the vco frequency has stabilized (locked), since no data output has been performed since the divisor n was changed the unlocked state data remains in the unlocked state. as a result, even though the frequency has stabilized (locked), the system remains (from the standpoint of the data) in the unlocked state. therefore, the unlocked state data acquired at data output (1), which occurs immediately after the divisor n was changed, should be treated as a dummy data output and ignored. the second data output (data output (2)) and following outputs are valid data. vco unlock l.p.f ? ? n unlock detection circuit ? r preset vco/n fref data output (2) data input data output (1) new data old data vco frequency locked locked unlocked ? error n unlock detection pin output unlock (ul) serial data output ce valid data can be output at intervals of one reference frequency period or longer. *: locking state determination is more reliable if it is based on reading valid output data several times wait for at least two reference frequency periods. divisor n modification ( data in p ut ) locked * no yes valid data output dummy data output
lc72131k, LC72131KMA no.a0788-18/22 directly outputting unlocked state data from the do pin (set by the do pin control data) since the unlocked state (high=locked, low=unlocked) is output directly from the do pin, the dummy data processing described in section 3 above is not required. after changing the divisor n, the locking state can be checked after waiting at least two reference frequency periods. clock time base usage notes the pull-up resistor used on the clock time base output pin ( bo1 ) should be at least 100k ? . this is to prevent degrading the vco c/n characteristics when a loop filter is formed using the built-in low-pass filter transistor. since the clock time base output pin and the low-pass filter have a common ground internal to the ic, it is necessary to minimize the time base output pin current fluctuations and to suppress their influence on the low-pass filter. also, to prevent chattering we recommend using a schmitt input at th e controller (microprocessor) that receives this signal. other items [1] notes on the phase comparator dead zone dz1 dz0 dead zone mode charge pump dead zone 0 0 dza on/on - -0s 0 1 dzb on/on -0s 1 0 dzc off/off +0s 1 1 dzd off/off ++0s since correction pulses are output from the charge pump even if the pll is lock ed when the charge pump is in the on/on state, the loop can easily become unstable. this point requires special care when designing application circuits. the following problems may occur in the on/on state. (1) side band generation due to reference frequency leakage (2) side band generation due to both the correction pulse envelope and low frequency leakage schemes in which a dead zone is present (off/off) have good loop stability, but have the problem that acquiring a high c/n ratio can be difficult. on the other hand, although it is easy to acquire a high c/n ratio with schemes in which there is no dead zone, it is difficult to achieve high loop stability. therefore, it can be effective to select dza or dzb, which have no dead zone, in applications which require an fm s/n ratio in excess of 90 to 100db, or in which an increased am stereo pilot margin is desired. on the other hand, we recommend selecting dzc or dzd, which provide a dead zone, for applications which do not require such a high fm signal-to-noise ratio and in which either am stereo is not used or an adequate am stereo pilo t margin can be achieved. v cc vco vt v dd pd ain aout bo1 rt ? 100k ?
lc72131k, LC72131KMA no.a0788-19/22 dead zone the phase comparator compares fp to a reference frequency (fr) as shown in figure 1. although the characteristics of this circuit (see figure 2) are such that the output voltage is proportional to the phase difference ? (line a), a region (the dead zone) in which it is not po ssible to compare small phase differences occurs in actual ics due to internal circuit delays and other factors (line b). a dead zone as small as possible is desirable for products that must provide a high s/n ratio. however, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. this is because it is possible for rf signals to leak from the mixer to the vco and modulate the vco in popularly-priced products in the presence of strong rf inputs. when the dead zone is narrow, the circuit outputs correction pulses and this output can further modulate the vco and generate beat frequencies with the rf signal. [2] notes on the fmin, amin, and ifin pins coupling capacitors must be placed as close as possible to their respective pin. a cap acitance of about 100pf is desirable. in particular, if a capacitan ce of 1000pf or over is used for the if pin, the time to reach the bias level will increase and incorrect counting may occur due to the relationship with the wait time. [3] notes on if counting ? sd must be used in conjunction with the if counting time when using if counting, always implement if counting by having the microprocesso r determine the presence of the if-ic sd (station detect) signal and turn on the if counter buffer only if the sd signal is present. schemes in which auto-searches are performed with only if counting are not recommended, since they can cause false detection where there is no signal due to overflow from the if counter buffer. [4] do pin usage techniques in addition to data output mode times, the do pin can also be used to check for if counter count completion and for unlock detection output. also, an input pin state can be output unchanged through the do pin and input to the controller. pin states after the power on reset [lc72131k] reference divider vco lpf programmable divider phase detector figure 1 mix rf signal leak fr fp figure 2 ? (ns) v (a) (b) dead zone open v ss aout ain pd xout v dd lc72131k fmin amin io2 ifin io1 bo4 bo3 bo2 bo1 do cl di xin ce input port open open open open input port nc nc
lc72131k, LC72131KMA no.a0788-20/22 pin states after the power on reset [LC72131KMA] application system example [lc72131k] input port v ss aout ain pd xout v dd LC72131KMA fmin amin io2 ifin io1 bo4 bo3 bo2 bo1 do cl di xin ce open input port open open open open 2 3 4 5 6 7 8 9 10 11 12 s s s s lc72131k v cc ifin am/fm-if tuner-system mono/st fm/am if-request st-indicate tune io1 bo4 bo3 bo2 bo1 do cl di ce xin nc do cl ? -com ce di unlock tune end-uc ifcount st-indic fmvco amvco s 1 13 io2 14 nc 15 amin 16 fmin 17 v dd 18 pd 19 ain 20 aout 21 v ss 22 xout
lc72131k, LC72131KMA no.a0788-21/22 application system example [LC72131KMA] 2 3 4 5 6 7 8 9 10 11 s s s s LC72131KMA v cc ifin am/fm-if tuner-system mono/st fm/am if-request st-indicate tune io1 bo4 bo3 bo2 bo1 do cl di ce xin do cl ? -com ce di unlock tune end-uc ifcount st-indic fmvco amvco s 1 12 io2 13 amin 14 fmin 15 v dd 16 pd 17 ain 18 aout 19 v ss 20 xout
lc72131k, LC72131KMA no.a0788-22/22 ps this catalog provides information as of october, 2012. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.

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